| Plenary Session |
| 8:00 |
Registration Opens |
| 9:00 – 9:10 |
Welcome Remark |
Rick Cassidy |
| 9:10 – 9:40 |
TSMC and its Ecosystem for Innovation |
Shang-Yi Chiang |
| 9:40 – 10:00 |
Coffee Break |
| 10:00 – 10:30 |
Partner Feature Talk - ARM |
Mike Inglis |
| 10:30 – 11:00 |
Partner Feature Talk - Synopsys |
Aart de Geus |
| 11:00 – 11:30 |
Partner Feature Talk - Cadence |
Lip-Bu Tan |
| 11:30 – 12:00 |
Partner Feature Talk - Mentor Graphics |
Wally Rhines |
| 12:00 – 13:00 |
Lunch |
| |
IP Track |
EDA Track |
IP/EDA/Services Track |
| 13:00 – 13:30 |
A comprehensive soft IP qualification system
Atrenta |
System-level hardware and software design applied to TSMC 28nm RF12
Synopsys |
Performance , Power, Area and Yield : From early design evaluation to production - Using ARM CPU core as a testing vehicle
GUC |
| 13:30 – 14:00 |
Innovative design of ultra low-power islets
Dolphin Integration |
A Substrate Noise Analysis and RLCK Extraction Flow for RF & High-Speed Design
Helic |
Differentiated Solutions built on TSMC technologies
eSilicon |
| 14:00 – 14:30 |
An Essential 1T-OTP NVM Component for IC Design
Sidense |
Using Clock Concurrent Optimization to improve PPA on ARM A9 Cortex Cores
Cadence |
IMEC's VCA Technology Targeting Services
IMEC |
| 14:30 – 15:00 |
An Introduction to ARM's Hard Macro Roadmap for Advanced TSMC Processes
ARM |
iLVS: Accessible, Supportable Paradigm for Circuit Verification at Advanced Node
Mentor |
Advancing System-Level Design: Simplifying SoC Complexity and Increasing Integration
Sonics |
| 15:00 – 15:30 |
Coffee Break |
| 15:30 – 16:00 |
3D Stacking of DRAM: Why Wide-IO is driving TSV
Cadence |
How to Design Analog/Mixed-signal at Advanced Node?
Cadence |
Designing at 2x Nanometers, Some New Problems and Some of the Same
Synopsys |
| 16:00 – 16:30 |
Latch-up immune ESD Protection Clamp for High Voltage optimized on TSMC BCD technology
Sofics |
Emerging Challenges for Power, Signal, and Reliability Verification on 3D-IC/Silicon Interposer Designs
Apache |
Keys to Successful DFM Partnership
Mentor / CSR |
| 16:30 – 17:00 |
Embedded Wisely, Embedded Widely in More-than-Moore
eMemory |
Challenges and Directions for Next Generation 3D-IC
Mentor / Qualcomm |
Constraint-Driven Design for Layout Dependent Effects in TSMC 28nm High Performance CMOS Technology
Solido / Springsoft |
| 17:00 – 17:30 |
Using High-Performance Interface IP and Moore's Law to Overcome Bandwidth Limitations for the Next-Generation of Tablets
Synopsys |
Using Design Specific Stage-based OCV
CLK DA |
Improving Analog/Mixed Signal Circuit Reliability at Advanced Nodes
Mentor |
| 17:30 – 18:30 |
Networking and Reception |
